Method and structure for retarding high temperature agglomeration of silicides using alloys

Method and structure for retarding high temperature agglomeration of silicides using alloys

Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CARRUTHERS ROY ARTHUR, KOZLOWSKI PAUL MICHAEL, NEWBURY JOSEPH SCOTT, ROY RONNEN ANDREW, LAVOIE CHRISTIAN, HARPER JAMES MCKELL EDWIN, CABRAL CYRIL
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.