Package with low stress hermetic seal

Package with low stress hermetic seal

A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periph...

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Hauptverfasser: GOLDMANN LEWIS SIGMUND, TOY HILTON T, SHERIF RAED A, PERFECTO ERIC DANIEL, SHUTLER WILLIAM FREDERICK
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator GOLDMANN LEWIS SIGMUND
TOY HILTON T
SHERIF RAED A
PERFECTO ERIC DANIEL
SHUTLER WILLIAM FREDERICK
description A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2002090761A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2002090761A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2002090761A13</originalsourceid><addsrcrecordid>eNrjZFANSEzOTkxPVSjPLMlQyMkvVyguKUotLlbISC3KTS3JTFYoTk3M4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgYGRgaWBuZmho6GxsSpAgDJRCfq</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Package with low stress hermetic seal</title><source>esp@cenet</source><creator>GOLDMANN LEWIS SIGMUND ; TOY HILTON T ; SHERIF RAED A ; PERFECTO ERIC DANIEL ; SHUTLER WILLIAM FREDERICK</creator><creatorcontrib>GOLDMANN LEWIS SIGMUND ; TOY HILTON T ; SHERIF RAED A ; PERFECTO ERIC DANIEL ; SHUTLER WILLIAM FREDERICK</creatorcontrib><description>A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020711&amp;DB=EPODOC&amp;CC=US&amp;NR=2002090761A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020711&amp;DB=EPODOC&amp;CC=US&amp;NR=2002090761A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GOLDMANN LEWIS SIGMUND</creatorcontrib><creatorcontrib>TOY HILTON T</creatorcontrib><creatorcontrib>SHERIF RAED A</creatorcontrib><creatorcontrib>PERFECTO ERIC DANIEL</creatorcontrib><creatorcontrib>SHUTLER WILLIAM FREDERICK</creatorcontrib><title>Package with low stress hermetic seal</title><description>A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFANSEzOTkxPVSjPLMlQyMkvVyguKUotLlbISC3KTS3JTFYoTk3M4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgYGRgaWBuZmho6GxsSpAgDJRCfq</recordid><startdate>20020711</startdate><enddate>20020711</enddate><creator>GOLDMANN LEWIS SIGMUND</creator><creator>TOY HILTON T</creator><creator>SHERIF RAED A</creator><creator>PERFECTO ERIC DANIEL</creator><creator>SHUTLER WILLIAM FREDERICK</creator><scope>EVB</scope></search><sort><creationdate>20020711</creationdate><title>Package with low stress hermetic seal</title><author>GOLDMANN LEWIS SIGMUND ; TOY HILTON T ; SHERIF RAED A ; PERFECTO ERIC DANIEL ; SHUTLER WILLIAM FREDERICK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2002090761A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GOLDMANN LEWIS SIGMUND</creatorcontrib><creatorcontrib>TOY HILTON T</creatorcontrib><creatorcontrib>SHERIF RAED A</creatorcontrib><creatorcontrib>PERFECTO ERIC DANIEL</creatorcontrib><creatorcontrib>SHUTLER WILLIAM FREDERICK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GOLDMANN LEWIS SIGMUND</au><au>TOY HILTON T</au><au>SHERIF RAED A</au><au>PERFECTO ERIC DANIEL</au><au>SHUTLER WILLIAM FREDERICK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Package with low stress hermetic seal</title><date>2002-07-11</date><risdate>2002</risdate><abstract>A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Package with low stress hermetic seal
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T00%3A23%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GOLDMANN%20LEWIS%20SIGMUND&rft.date=2002-07-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2002090761A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true