Method for manufacturing semiconductor integrated circuit and semiconductor integrated circuit manufactured by this method

A semiconductor integrated circuit is provided in which the transistor size can be minimized by only changing one mask after the performance of a prototype is tested. Impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines and portions surrounded by broken...

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1. Verfasser: ONO YOSHITERU
Format: Patent
Sprache:eng
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Zusammenfassung:A semiconductor integrated circuit is provided in which the transistor size can be minimized by only changing one mask after the performance of a prototype is tested. Impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines and portions surrounded by broken lines) surrounded by a field insulating film on a semiconductor substrate for prototyping, and a prototype semiconductor integrated circuit is thereby manufactured, and then testing is performed. When the prototype semiconductor integrated circuit operates in a desired manner, impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines only) surrounded by a field insulating film on a semiconductor substrate for shipment, and a semiconductor integrated circuit for shipment is thereby manufactured.