Method of forming an alignment feature in or on a multi-layered semiconductor structure
A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited th...
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| creator | FARROW REGINALD C BOULIN DAVID M KIZILYALLI ISIK C LAYADI NACE MKRTCHYAN MASIS |
| description | A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2002004283A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2002004283A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2002004283A13</originalsourceid><addsrcrecordid>eNqNi7EKAjEQRK-xEPUfFqwPzjsLWxHFxkrF8liSzRlIdo9kU_j3pvADhIEZeG-WzetG-hYL4sBJip4nQAYMfuJIrOAItSQCzyAJpCKIJahvA34okYVM0RthW4xWIWuqox7WzcJhyLT59arZXs6P07WlWUbKMxpi0vF577uuZt8fhuNu-M_6AjGzOuI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming an alignment feature in or on a multi-layered semiconductor structure</title><source>esp@cenet</source><creator>FARROW REGINALD C ; BOULIN DAVID M ; KIZILYALLI ISIK C ; LAYADI NACE ; MKRTCHYAN MASIS</creator><creatorcontrib>FARROW REGINALD C ; BOULIN DAVID M ; KIZILYALLI ISIK C ; LAYADI NACE ; MKRTCHYAN MASIS</creatorcontrib><description>A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.</description><edition>7</edition><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CINEMATOGRAPHY ; ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020110&DB=EPODOC&CC=US&NR=2002004283A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020110&DB=EPODOC&CC=US&NR=2002004283A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FARROW REGINALD C</creatorcontrib><creatorcontrib>BOULIN DAVID M</creatorcontrib><creatorcontrib>KIZILYALLI ISIK C</creatorcontrib><creatorcontrib>LAYADI NACE</creatorcontrib><creatorcontrib>MKRTCHYAN MASIS</creatorcontrib><title>Method of forming an alignment feature in or on a multi-layered semiconductor structure</title><description>A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CINEMATOGRAPHY</subject><subject>ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKAjEQRK-xEPUfFqwPzjsLWxHFxkrF8liSzRlIdo9kU_j3pvADhIEZeG-WzetG-hYL4sBJip4nQAYMfuJIrOAItSQCzyAJpCKIJahvA34okYVM0RthW4xWIWuqox7WzcJhyLT59arZXs6P07WlWUbKMxpi0vF577uuZt8fhuNu-M_6AjGzOuI</recordid><startdate>20020110</startdate><enddate>20020110</enddate><creator>FARROW REGINALD C</creator><creator>BOULIN DAVID M</creator><creator>KIZILYALLI ISIK C</creator><creator>LAYADI NACE</creator><creator>MKRTCHYAN MASIS</creator><scope>EVB</scope></search><sort><creationdate>20020110</creationdate><title>Method of forming an alignment feature in or on a multi-layered semiconductor structure</title><author>FARROW REGINALD C ; BOULIN DAVID M ; KIZILYALLI ISIK C ; LAYADI NACE ; MKRTCHYAN MASIS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2002004283A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CINEMATOGRAPHY</topic><topic>ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FARROW REGINALD C</creatorcontrib><creatorcontrib>BOULIN DAVID M</creatorcontrib><creatorcontrib>KIZILYALLI ISIK C</creatorcontrib><creatorcontrib>LAYADI NACE</creatorcontrib><creatorcontrib>MKRTCHYAN MASIS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FARROW REGINALD C</au><au>BOULIN DAVID M</au><au>KIZILYALLI ISIK C</au><au>LAYADI NACE</au><au>MKRTCHYAN MASIS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming an alignment feature in or on a multi-layered semiconductor structure</title><date>2002-01-10</date><risdate>2002</risdate><abstract>A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES |
| title | Method of forming an alignment feature in or on a multi-layered semiconductor structure |
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