Method of reducing test time for NVM cell-based FPGAs

The present invention provides for a method of testing an FPGA using NVM memory cells for programmable interconnects. The NVM memory cells are arranged as a memory array of rows and columns. User-configurable logic elements and interconnections, which are programmed by the stored states of the memor...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SAXE TIMOTHY, HECHT VOLKER
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING
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