Integrated circuit having a comparator circuit including at least one differential amplifier
An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2,...
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creator | YANO YUKIO |
description | An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor 1, a MOS transistor 2 constituting an input section, and a MOS transistor 10 constituting an output section. The current path L1 of the differential amplifier circuit D1 includes a load MOS transistor 11, an amplifying depletion type MOS transistor 13, and an input terminal in1. Similarly, the current path L2 includes a load MOS transistor 12, an amplifying depletion type MOS transistor 14, and an input terminal in2. The inverter INV is constructed with a load MOS transistor 3 and a switching transistor 4. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2001010479A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2001010479A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2001010479A13</originalsourceid><addsrcrecordid>eNqNyjELwjAQhuEsDqL-hwNnoVVBOoooOqubUI7kUg_SS0iu_n6LiLN8wzs839Q8LqLUZVRyYDnbgRWe-GLpAMHGPuFoMf-MxYbBfVghEBaFKASOvadMoowBsE-BPVOem4nHUGjx7cwsT8fb4byiFFsqCS0JaXu_rquqHrfdNft689_rDdXwPR0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit having a comparator circuit including at least one differential amplifier</title><source>esp@cenet</source><creator>YANO YUKIO</creator><creatorcontrib>YANO YUKIO</creatorcontrib><description>An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor 1, a MOS transistor 2 constituting an input section, and a MOS transistor 10 constituting an output section. The current path L1 of the differential amplifier circuit D1 includes a load MOS transistor 11, an amplifying depletion type MOS transistor 13, and an input terminal in1. Similarly, the current path L2 includes a load MOS transistor 12, an amplifying depletion type MOS transistor 14, and an input terminal in2. The inverter INV is constructed with a load MOS transistor 3 and a switching transistor 4.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010802&DB=EPODOC&CC=US&NR=2001010479A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010802&DB=EPODOC&CC=US&NR=2001010479A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YANO YUKIO</creatorcontrib><title>Integrated circuit having a comparator circuit including at least one differential amplifier</title><description>An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor 1, a MOS transistor 2 constituting an input section, and a MOS transistor 10 constituting an output section. The current path L1 of the differential amplifier circuit D1 includes a load MOS transistor 11, an amplifying depletion type MOS transistor 13, and an input terminal in1. Similarly, the current path L2 includes a load MOS transistor 12, an amplifying depletion type MOS transistor 14, and an input terminal in2. The inverter INV is constructed with a load MOS transistor 3 and a switching transistor 4.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjELwjAQhuEsDqL-hwNnoVVBOoooOqubUI7kUg_SS0iu_n6LiLN8wzs839Q8LqLUZVRyYDnbgRWe-GLpAMHGPuFoMf-MxYbBfVghEBaFKASOvadMoowBsE-BPVOem4nHUGjx7cwsT8fb4byiFFsqCS0JaXu_rquqHrfdNft689_rDdXwPR0</recordid><startdate>20010802</startdate><enddate>20010802</enddate><creator>YANO YUKIO</creator><scope>EVB</scope></search><sort><creationdate>20010802</creationdate><title>Integrated circuit having a comparator circuit including at least one differential amplifier</title><author>YANO YUKIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2001010479A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>YANO YUKIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YANO YUKIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit having a comparator circuit including at least one differential amplifier</title><date>2001-08-02</date><risdate>2001</risdate><abstract>An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor 1, a MOS transistor 2 constituting an input section, and a MOS transistor 10 constituting an output section. The current path L1 of the differential amplifier circuit D1 includes a load MOS transistor 11, an amplifying depletion type MOS transistor 13, and an input terminal in1. Similarly, the current path L2 includes a load MOS transistor 12, an amplifying depletion type MOS transistor 14, and an input terminal in2. The inverter INV is constructed with a load MOS transistor 3 and a switching transistor 4.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | Integrated circuit having a comparator circuit including at least one differential amplifier |
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