Instruction and micro-architecture support for decompression on core

Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more l...

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Bibliographische Detailangaben

Hauptverfasser:	Subramoney, Sreenivas, Feghali, Wajdi, Gopal, Vinodh, Gaur, Jayesh, Shanbhogue, Vedvyas, Chauhan, Adarsh
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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