Reduction of latency impact of on-die error checking and correction (ECC)

A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device...

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Hauptverfasser:	Lanka, Narasimha, Bains, Kuljit S
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Lanka, Narasimha Bains, Kuljit S
description	A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.
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title	Reduction of latency impact of on-die error checking and correction (ECC)
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