3D chip package based on vertical-through-via connector

A connector may include: a first substrate having a top surface, a bottom surface opposite to the top surface of the top substrate and a side surface joining an edge of the top surface of the first substrate and joining an edge of the bottom surface of the first substrate; a second substrate having...

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Bibliographische Detailangaben

Hauptverfasser:	Lo, Hsin-Jung, Lin, Mou-Shiung, Chou, Chiu-Ming, Yang, Ping-Jung, Lee, Jin-Yuan
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES
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