Connecting multiple chips using an interconnect device
Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a...
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| creator | Haba, Belgacem Delacruz, Javier A |
| description | Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip. |
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In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. 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In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBzzs_LS00uycxLV8gtzSnJLMhJVUjOyCwoVigtBgkm5ilk5pWkFiVD1CmkpJZlJqfyMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JL40GBDI0NTEwtTCycjY2LUAADJZi4R</recordid><startdate>20241126</startdate><enddate>20241126</enddate><creator>Haba, Belgacem</creator><creator>Delacruz, Javier A</creator><scope>EVB</scope></search><sort><creationdate>20241126</creationdate><title>Connecting multiple chips using an interconnect device</title><author>Haba, Belgacem ; Delacruz, Javier A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12154858B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Haba, Belgacem</creatorcontrib><creatorcontrib>Delacruz, Javier A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Haba, Belgacem</au><au>Delacruz, Javier A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Connecting multiple chips using an interconnect device</title><date>2024-11-26</date><risdate>2024</risdate><abstract>Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Connecting multiple chips using an interconnect device |
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