Signal envelope detector, overload detector, receiver, base station and mobile device
A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage di...
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creator | Clara, Martin Cascio, Giacomo |
description | A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12143073B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12143073B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12143073B23</originalsourceid><addsrcrecordid>eNqNizELwjAUBrM4iPofnnsF2wjuiuJeO5fX5LMEYl5IQn6_Cg6OTgfH3VINvZsDe0Ko8BJBFgWmSGpIKpIXtj8qwcC9dUMTZ1AuXJwE4mDpKZPzn706g7VaPNhnbL5cqe31cj_fdogyIkc2CCjj0Ldde9D7oz51-p_mBb4zOPc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Signal envelope detector, overload detector, receiver, base station and mobile device</title><source>esp@cenet</source><creator>Clara, Martin ; Cascio, Giacomo</creator><creatorcontrib>Clara, Martin ; Cascio, Giacomo</creatorcontrib><description>A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.</description><language>eng</language><subject>AMPLIFIERS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241112&DB=EPODOC&CC=US&NR=12143073B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241112&DB=EPODOC&CC=US&NR=12143073B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Clara, Martin</creatorcontrib><creatorcontrib>Cascio, Giacomo</creatorcontrib><title>Signal envelope detector, overload detector, receiver, base station and mobile device</title><description>A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizELwjAUBrM4iPofnnsF2wjuiuJeO5fX5LMEYl5IQn6_Cg6OTgfH3VINvZsDe0Ko8BJBFgWmSGpIKpIXtj8qwcC9dUMTZ1AuXJwE4mDpKZPzn706g7VaPNhnbL5cqe31cj_fdogyIkc2CCjj0Ldde9D7oz51-p_mBb4zOPc</recordid><startdate>20241112</startdate><enddate>20241112</enddate><creator>Clara, Martin</creator><creator>Cascio, Giacomo</creator><scope>EVB</scope></search><sort><creationdate>20241112</creationdate><title>Signal envelope detector, overload detector, receiver, base station and mobile device</title><author>Clara, Martin ; Cascio, Giacomo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12143073B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>Clara, Martin</creatorcontrib><creatorcontrib>Cascio, Giacomo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Clara, Martin</au><au>Cascio, Giacomo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Signal envelope detector, overload detector, receiver, base station and mobile device</title><date>2024-11-12</date><risdate>2024</risdate><abstract>A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | AMPLIFIERS BASIC ELECTRONIC CIRCUITRY ELECTRICITY |
title | Signal envelope detector, overload detector, receiver, base station and mobile device |
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