Strap technology to improve ESD HBM performance
The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active...
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| creator | Chen, Pin-Chen Jong, Yu-Chang Huang, Lin-Yu Hsu, Sheng-Fu Hsu, Hao-Hua Huang, Hsiao-Ching |
| description | The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12132042B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12132042B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12132042B23</originalsourceid><addsrcrecordid>eNrjZNAPLilKLFAoSU3OyMvPyU-vVCjJV8jMLSjKL0tVcA12UfBw8lUoSC1Kyy_KTcxLTuVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYZGhsZGBiZGTkbGxKgBAO8hKlg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Strap technology to improve ESD HBM performance</title><source>esp@cenet</source><creator>Chen, Pin-Chen ; Jong, Yu-Chang ; Huang, Lin-Yu ; Hsu, Sheng-Fu ; Hsu, Hao-Hua ; Huang, Hsiao-Ching</creator><creatorcontrib>Chen, Pin-Chen ; Jong, Yu-Chang ; Huang, Lin-Yu ; Hsu, Sheng-Fu ; Hsu, Hao-Hua ; Huang, Hsiao-Ching</creatorcontrib><description>The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241029&DB=EPODOC&CC=US&NR=12132042B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241029&DB=EPODOC&CC=US&NR=12132042B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chen, Pin-Chen</creatorcontrib><creatorcontrib>Jong, Yu-Chang</creatorcontrib><creatorcontrib>Huang, Lin-Yu</creatorcontrib><creatorcontrib>Hsu, Sheng-Fu</creatorcontrib><creatorcontrib>Hsu, Hao-Hua</creatorcontrib><creatorcontrib>Huang, Hsiao-Ching</creatorcontrib><title>Strap technology to improve ESD HBM performance</title><description>The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPLilKLFAoSU3OyMvPyU-vVCjJV8jMLSjKL0tVcA12UfBw8lUoSC1Kyy_KTcxLTuVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYZGhsZGBiZGTkbGxKgBAO8hKlg</recordid><startdate>20241029</startdate><enddate>20241029</enddate><creator>Chen, Pin-Chen</creator><creator>Jong, Yu-Chang</creator><creator>Huang, Lin-Yu</creator><creator>Hsu, Sheng-Fu</creator><creator>Hsu, Hao-Hua</creator><creator>Huang, Hsiao-Ching</creator><scope>EVB</scope></search><sort><creationdate>20241029</creationdate><title>Strap technology to improve ESD HBM performance</title><author>Chen, Pin-Chen ; Jong, Yu-Chang ; Huang, Lin-Yu ; Hsu, Sheng-Fu ; Hsu, Hao-Hua ; Huang, Hsiao-Ching</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12132042B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chen, Pin-Chen</creatorcontrib><creatorcontrib>Jong, Yu-Chang</creatorcontrib><creatorcontrib>Huang, Lin-Yu</creatorcontrib><creatorcontrib>Hsu, Sheng-Fu</creatorcontrib><creatorcontrib>Hsu, Hao-Hua</creatorcontrib><creatorcontrib>Huang, Hsiao-Ching</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, Pin-Chen</au><au>Jong, Yu-Chang</au><au>Huang, Lin-Yu</au><au>Hsu, Sheng-Fu</au><au>Hsu, Hao-Hua</au><au>Huang, Hsiao-Ching</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Strap technology to improve ESD HBM performance</title><date>2024-10-29</date><risdate>2024</risdate><abstract>The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Strap technology to improve ESD HBM performance |
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