Fabrication of gate-all-around integrated circuit structures having additive metal gates
Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertica...
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creator | Crum, Dax M Golonzka, Oleg Ghani, Tahir Lavric, Dan S Saadat, Omair |
description | Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12113068B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12113068B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12113068B23</originalsourceid><addsrcrecordid>eNqNjEEKwjAQAHPxIOof1gcETAviWbF4V8FbWZNtuhCTkmz6fkV8gKeBYZilenT4zGxROEVIA3gU0hiCxpxqdMBRyOePdGA528oCRXK1UjMVGHHm6AGdY-GZ4EWC4fsoa7UYMBTa_LhS2-58O100TamnMqGlSNLfr6Yxpt3tD8em_ad5A9hlOt8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Fabrication of gate-all-around integrated circuit structures having additive metal gates</title><source>esp@cenet</source><creator>Crum, Dax M ; Golonzka, Oleg ; Ghani, Tahir ; Lavric, Dan S ; Saadat, Omair</creator><creatorcontrib>Crum, Dax M ; Golonzka, Oleg ; Ghani, Tahir ; Lavric, Dan S ; Saadat, Omair</creatorcontrib><description>Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES ; NANOTECHNOLOGY ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES ; TRANSPORTING</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241008&DB=EPODOC&CC=US&NR=12113068B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241008&DB=EPODOC&CC=US&NR=12113068B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Crum, Dax M</creatorcontrib><creatorcontrib>Golonzka, Oleg</creatorcontrib><creatorcontrib>Ghani, Tahir</creatorcontrib><creatorcontrib>Lavric, Dan S</creatorcontrib><creatorcontrib>Saadat, Omair</creatorcontrib><title>Fabrication of gate-all-around integrated circuit structures having additive metal gates</title><description>Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</subject><subject>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</subject><subject>NANOTECHNOLOGY</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjEEKwjAQAHPxIOof1gcETAviWbF4V8FbWZNtuhCTkmz6fkV8gKeBYZilenT4zGxROEVIA3gU0hiCxpxqdMBRyOePdGA528oCRXK1UjMVGHHm6AGdY-GZ4EWC4fsoa7UYMBTa_LhS2-58O100TamnMqGlSNLfr6Yxpt3tD8em_ad5A9hlOt8</recordid><startdate>20241008</startdate><enddate>20241008</enddate><creator>Crum, Dax M</creator><creator>Golonzka, Oleg</creator><creator>Ghani, Tahir</creator><creator>Lavric, Dan S</creator><creator>Saadat, Omair</creator><scope>EVB</scope></search><sort><creationdate>20241008</creationdate><title>Fabrication of gate-all-around integrated circuit structures having additive metal gates</title><author>Crum, Dax M ; Golonzka, Oleg ; Ghani, Tahir ; Lavric, Dan S ; Saadat, Omair</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12113068B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</topic><topic>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</topic><topic>NANOTECHNOLOGY</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Crum, Dax M</creatorcontrib><creatorcontrib>Golonzka, Oleg</creatorcontrib><creatorcontrib>Ghani, Tahir</creatorcontrib><creatorcontrib>Lavric, Dan S</creatorcontrib><creatorcontrib>Saadat, Omair</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Crum, Dax M</au><au>Golonzka, Oleg</au><au>Ghani, Tahir</au><au>Lavric, Dan S</au><au>Saadat, Omair</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Fabrication of gate-all-around integrated circuit structures having additive metal gates</title><date>2024-10-08</date><risdate>2024</risdate><abstract>Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OR TREATMENT OF NANOSTRUCTURES MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES NANOTECHNOLOGY PERFORMING OPERATIONS SEMICONDUCTOR DEVICES SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES TRANSPORTING |
title | Fabrication of gate-all-around integrated circuit structures having additive metal gates |
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