Programmable coarse grained and sparse matrix compute hardware with advanced scheduling
One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of spar...
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| creator | Chen, Xiaoming Gottschlich, Justin E Ould-Ahmed-Vall, Elmoustapha Yao, Anbang Satish, Nadathur Rajagopalan Galoppo Von Borries, Nicolas C Nurvitadhi, Eriko Akhbari, Farshad Baghsorkhi, Sara S Chen, Feng Lin, Tsung-Han Koker, Altug Kim, Dukhwan Nealis, Kevin Sinha, Kamal Vembu, Balaji Srinivasa, Narayan Bottleson, Jeremy Barik, Rajkishore |
| description | One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity. |
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| subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS |
| title | Programmable coarse grained and sparse matrix compute hardware with advanced scheduling |
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