Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module

Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module

A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed withi...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Malone, Douglas J, Arp, Andreas H. A, Frankel, Jason Lee, Baez, Franklin M, Marquart, Chad Andrew, Dreps, Daniel M, Tong, Ching Lung, Zhang, Lily Jielu
Format: Patent
Sprache:eng
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Beschreibung
Zusammenfassung:A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.