SRAM speed and margin optimization via spacer tuning
An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surfa...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Su, Hsin-Wen Lin, Chien-Chih Lim, Kian-Long Yang, Chih-Chuan Lin, Shih-Hao |
| description | An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12101921B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12101921B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12101921B23</originalsourceid><addsrcrecordid>eNrjZDAJDnL0VSguSE1NUUjMS1HITSxKz8xTyC8oyczNrEosyczPUyjLTASqSExOLVIoKc3LzEvnYWBNS8wpTuWF0twMim6uIc4euqkF-fGpYKV5qSXxocGGRoYGhpZGhk5GxsSoAQD6iyyA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SRAM speed and margin optimization via spacer tuning</title><source>esp@cenet</source><creator>Su, Hsin-Wen ; Lin, Chien-Chih ; Lim, Kian-Long ; Yang, Chih-Chuan ; Lin, Shih-Hao</creator><creatorcontrib>Su, Hsin-Wen ; Lin, Chien-Chih ; Lim, Kian-Long ; Yang, Chih-Chuan ; Lin, Shih-Hao</creatorcontrib><description>An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240924&DB=EPODOC&CC=US&NR=12101921B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240924&DB=EPODOC&CC=US&NR=12101921B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Su, Hsin-Wen</creatorcontrib><creatorcontrib>Lin, Chien-Chih</creatorcontrib><creatorcontrib>Lim, Kian-Long</creatorcontrib><creatorcontrib>Yang, Chih-Chuan</creatorcontrib><creatorcontrib>Lin, Shih-Hao</creatorcontrib><title>SRAM speed and margin optimization via spacer tuning</title><description>An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAJDnL0VSguSE1NUUjMS1HITSxKz8xTyC8oyczNrEosyczPUyjLTASqSExOLVIoKc3LzEvnYWBNS8wpTuWF0twMim6uIc4euqkF-fGpYKV5qSXxocGGRoYGhpZGhk5GxsSoAQD6iyyA</recordid><startdate>20240924</startdate><enddate>20240924</enddate><creator>Su, Hsin-Wen</creator><creator>Lin, Chien-Chih</creator><creator>Lim, Kian-Long</creator><creator>Yang, Chih-Chuan</creator><creator>Lin, Shih-Hao</creator><scope>EVB</scope></search><sort><creationdate>20240924</creationdate><title>SRAM speed and margin optimization via spacer tuning</title><author>Su, Hsin-Wen ; Lin, Chien-Chih ; Lim, Kian-Long ; Yang, Chih-Chuan ; Lin, Shih-Hao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12101921B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Su, Hsin-Wen</creatorcontrib><creatorcontrib>Lin, Chien-Chih</creatorcontrib><creatorcontrib>Lim, Kian-Long</creatorcontrib><creatorcontrib>Yang, Chih-Chuan</creatorcontrib><creatorcontrib>Lin, Shih-Hao</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Su, Hsin-Wen</au><au>Lin, Chien-Chih</au><au>Lim, Kian-Long</au><au>Yang, Chih-Chuan</au><au>Lin, Shih-Hao</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SRAM speed and margin optimization via spacer tuning</title><date>2024-09-24</date><risdate>2024</risdate><abstract>An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US12101921B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | SRAM speed and margin optimization via spacer tuning |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T11%3A56%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Su,%20Hsin-Wen&rft.date=2024-09-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS12101921B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |