Stacked transistor chip package with source coupling

Stacked transistor chip package with source coupling

A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pa...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Yuferev, Sergey, Ng, Chee Yang, Palm, Petteri, Long, Theng Chao, Calo, Paul Armand Asentista, Maerz, Josef, Yong, Wae Chet
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.