Computing system with direct invalidation in a hierarchical cache structure based on at least one designated key identification code

A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back,...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Wang, Weilin, Guan, Yingbing, Yi, Lei
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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