Memory device with multiple input/output interfaces
A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further i...
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creator | Siau, Chang H Parry, Jonathan S |
description | A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane. |
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The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240903&DB=EPODOC&CC=US&NR=12079479B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240903&DB=EPODOC&CC=US&NR=12079479B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Siau, Chang H</creatorcontrib><creatorcontrib>Parry, Jonathan S</creatorcontrib><title>Memory device with multiple input/output interfaces</title><description>A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD2Tc3NL6pUSEkty0xOVSjPLMlQyC3NKcksyElVyMwrKC3Rzy8tAVJATklqUVpicmoxDwNrWmJOcSovlOZmUHRzDXH20E0tyI9PLS4AqslLLYkPDTY0MjC3NDG3dDIyJkYNAEELLUE</recordid><startdate>20240903</startdate><enddate>20240903</enddate><creator>Siau, Chang H</creator><creator>Parry, Jonathan S</creator><scope>EVB</scope></search><sort><creationdate>20240903</creationdate><title>Memory device with multiple input/output interfaces</title><author>Siau, Chang H ; Parry, Jonathan S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12079479B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Siau, Chang H</creatorcontrib><creatorcontrib>Parry, Jonathan S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Siau, Chang H</au><au>Parry, Jonathan S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory device with multiple input/output interfaces</title><date>2024-09-03</date><risdate>2024</risdate><abstract>A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Memory device with multiple input/output interfaces |
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