Cache line demote infrastructure for multi-processor pipelines

Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In s...

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Bibliographische Detailangaben

Hauptverfasser:	Maslekar, Omkar, Chamberlain, Jeffrey D, Autee, Priya, Verplanke, Edwin, Herdrich, Andrew J, Shah, Rahul R
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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