Methods of fabricating semiconductor package
Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barri...
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| creator | Park, Jung-Ho Jang, Jae Gwon Park, Jin-Woo Jeon, Gwang Jae |
| description | Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure. |
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The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240723&DB=EPODOC&CC=US&NR=12046526B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240723&DB=EPODOC&CC=US&NR=12046526B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Park, Jung-Ho</creatorcontrib><creatorcontrib>Jang, Jae Gwon</creatorcontrib><creatorcontrib>Park, Jin-Woo</creatorcontrib><creatorcontrib>Jeon, Gwang Jae</creatorcontrib><title>Methods of fabricating semiconductor package</title><description>Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDxTS3JyE8pVshPU0hLTCrKTE4sycxLVyhOzc1Mzs9LKU0uyS9SKEhMzk5MT-VhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQFWpeakl8aHBhkYGJmamRmZORsbEqAEArpkqKQ</recordid><startdate>20240723</startdate><enddate>20240723</enddate><creator>Park, Jung-Ho</creator><creator>Jang, Jae Gwon</creator><creator>Park, Jin-Woo</creator><creator>Jeon, Gwang Jae</creator><scope>EVB</scope></search><sort><creationdate>20240723</creationdate><title>Methods of fabricating semiconductor package</title><author>Park, Jung-Ho ; Jang, Jae Gwon ; Park, Jin-Woo ; Jeon, Gwang Jae</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12046526B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Park, Jung-Ho</creatorcontrib><creatorcontrib>Jang, Jae Gwon</creatorcontrib><creatorcontrib>Park, Jin-Woo</creatorcontrib><creatorcontrib>Jeon, Gwang Jae</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Park, Jung-Ho</au><au>Jang, Jae Gwon</au><au>Park, Jin-Woo</au><au>Jeon, Gwang Jae</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods of fabricating semiconductor package</title><date>2024-07-23</date><risdate>2024</risdate><abstract>Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Methods of fabricating semiconductor package |
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