Fast, energy efficient CMOS 2P1R1W register file array using harvested data

New CMOS harvesting circuits are proposed that improve 2-port/multiport Register File Array circuit speed and substantially lower the energy cost of moving data along local and global bitpaths when engaging harvested data to self-limit energy dissipation. The uncertainty in BL signal development due to statistical variations in cell read current is eliminated by self-disabling action in the selected cell when the electric potential of harvested data matches the BL voltage from signal development while demanding fewer peripheral circuit transistors per column than conventional sensing schemes. Proposed bit path circuits engage harvested charge to provide immunity to disturb current noise during concurrent Read and Write access along a WL-eliminating the performance, area and energy overheads of BL keeper circuits typically required in conventional Register File arrays. Proposed circuits improve the reliability of Read performance-limiting bitcell devices from voltage accelerated aging mechanisms by lowering of vertical and lateral electric fields across these cell transistors when holding harvested charge during most of active and standby periods. Register File bitcell transistor design trade-off constraints between array leakage in active mode and read current are considerably relaxed when engaging harvested charge enabling much higher read currents for any given total array leakage. Area overheads of proposed circuits are expected to be marginally lower based on device widths of replacements to conventional peripheral circuits and can be further minimized by sharing of devices and their connections between bit slices of the array peripheral circuits. Moreover, proposed circuits do not require any changes to the CMOS platform, to the bitcell or to the array architecture with much of the flow for design, verification and test of 2-Port/multiport RF Memory arrays expected to remain unchanged-minimizing risk and allowing integration of proposed circuits into existing products with minimal disruption to schedule and cost.