Interconnect architecture for three-dimensional processing systems
A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with...
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| creator | Jayasena, Nuwan S Eckert, Yasuko |
| description | A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12033714B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12033714B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12033714B23</originalsourceid><addsrcrecordid>eNrjZHDyzCtJLUrOz8tLTS5RSCxKzsgsAbJKi1IV0vKLFEoyilJTdVMyc1PzijPz8xJzFAqK8pNTi4sz89IViiuLS1Jzi3kYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGRgbGxuaGJk5ExMWoAyFczSg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Interconnect architecture for three-dimensional processing systems</title><source>esp@cenet</source><creator>Jayasena, Nuwan S ; Eckert, Yasuko</creator><creatorcontrib>Jayasena, Nuwan S ; Eckert, Yasuko</creatorcontrib><description>A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240709&DB=EPODOC&CC=US&NR=12033714B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240709&DB=EPODOC&CC=US&NR=12033714B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jayasena, Nuwan S</creatorcontrib><creatorcontrib>Eckert, Yasuko</creatorcontrib><title>Interconnect architecture for three-dimensional processing systems</title><description>A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDyzCtJLUrOz8tLTS5RSCxKzsgsAbJKi1IV0vKLFEoyilJTdVMyc1PzijPz8xJzFAqK8pNTi4sz89IViiuLS1Jzi3kYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGRgbGxuaGJk5ExMWoAyFczSg</recordid><startdate>20240709</startdate><enddate>20240709</enddate><creator>Jayasena, Nuwan S</creator><creator>Eckert, Yasuko</creator><scope>EVB</scope></search><sort><creationdate>20240709</creationdate><title>Interconnect architecture for three-dimensional processing systems</title><author>Jayasena, Nuwan S ; Eckert, Yasuko</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12033714B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Jayasena, Nuwan S</creatorcontrib><creatorcontrib>Eckert, Yasuko</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jayasena, Nuwan S</au><au>Eckert, Yasuko</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Interconnect architecture for three-dimensional processing systems</title><date>2024-07-09</date><risdate>2024</risdate><abstract>A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Interconnect architecture for three-dimensional processing systems |
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