Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost o...

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description A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p−−-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p−−-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p−−-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12027617B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12027617B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12027617B23</originalsourceid><addsrcrecordid>eNqNjE0KwjAUBrNxIeodngcQbAS7V1rcV9fl-fJFA01S8uP5RfAAXQ0Dw6wVBjc5iYGE09MZUIb_ualSYiKDjxMQB0Me5R0NRUueQ7UspSYXXpQXDLZqZXnK2P25Ufu-u19vB8xxRJ5ZEFDGx9Doo27PTXvRpyXNF4BKQAU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device</title><source>esp@cenet</source><creator>Kinoshita, Akimasa</creator><creatorcontrib>Kinoshita, Akimasa</creatorcontrib><description>A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p−−-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p−−-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p−−-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240702&amp;DB=EPODOC&amp;CC=US&amp;NR=12027617B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240702&amp;DB=EPODOC&amp;CC=US&amp;NR=12027617B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kinoshita, Akimasa</creatorcontrib><title>Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device</title><description>A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p−−-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p−−-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p−−-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjE0KwjAUBrNxIeodngcQbAS7V1rcV9fl-fJFA01S8uP5RfAAXQ0Dw6wVBjc5iYGE09MZUIb_ualSYiKDjxMQB0Me5R0NRUueQ7UspSYXXpQXDLZqZXnK2P25Ufu-u19vB8xxRJ5ZEFDGx9Doo27PTXvRpyXNF4BKQAU</recordid><startdate>20240702</startdate><enddate>20240702</enddate><creator>Kinoshita, Akimasa</creator><scope>EVB</scope></search><sort><creationdate>20240702</creationdate><title>Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device</title><author>Kinoshita, Akimasa</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12027617B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kinoshita, Akimasa</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kinoshita, Akimasa</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device</title><date>2024-07-02</date><risdate>2024</risdate><abstract>A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p−−-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p−−-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p−−-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T18%3A59%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kinoshita,%20Akimasa&rft.date=2024-07-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS12027617B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true