Lockstep comparators and related methods
Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic ha...
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| creator | Ghotgalkar, Shailesh Ganapat Suvarna, Rajeev Viswanathan Pillai, Prasanth Goud Langadi, Saya |
| description | Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12025659B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12025659B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12025659B23</originalsourceid><addsrcrecordid>eNrjZNDwyU_OLi5JLVBIzs8tSCxKLMkvKlZIzEtRKErNSSxJTVHITS3JyE8p5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhkYGRqZmppZORsbEqAEA8OIotw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Lockstep comparators and related methods</title><source>esp@cenet</source><creator>Ghotgalkar, Shailesh Ganapat ; Suvarna, Rajeev ; Viswanathan Pillai, Prasanth ; Goud Langadi, Saya</creator><creatorcontrib>Ghotgalkar, Shailesh Ganapat ; Suvarna, Rajeev ; Viswanathan Pillai, Prasanth ; Goud Langadi, Saya</creatorcontrib><description>Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; PULSE TECHNIQUE ; TESTING</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240702&DB=EPODOC&CC=US&NR=12025659B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240702&DB=EPODOC&CC=US&NR=12025659B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ghotgalkar, Shailesh Ganapat</creatorcontrib><creatorcontrib>Suvarna, Rajeev</creatorcontrib><creatorcontrib>Viswanathan Pillai, Prasanth</creatorcontrib><creatorcontrib>Goud Langadi, Saya</creatorcontrib><title>Lockstep comparators and related methods</title><description>Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDwyU_OLi5JLVBIzs8tSCxKLMkvKlZIzEtRKErNSSxJTVHITS3JyE8p5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhkYGRqZmppZORsbEqAEA8OIotw</recordid><startdate>20240702</startdate><enddate>20240702</enddate><creator>Ghotgalkar, Shailesh Ganapat</creator><creator>Suvarna, Rajeev</creator><creator>Viswanathan Pillai, Prasanth</creator><creator>Goud Langadi, Saya</creator><scope>EVB</scope></search><sort><creationdate>20240702</creationdate><title>Lockstep comparators and related methods</title><author>Ghotgalkar, Shailesh Ganapat ; Suvarna, Rajeev ; Viswanathan Pillai, Prasanth ; Goud Langadi, Saya</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12025659B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Ghotgalkar, Shailesh Ganapat</creatorcontrib><creatorcontrib>Suvarna, Rajeev</creatorcontrib><creatorcontrib>Viswanathan Pillai, Prasanth</creatorcontrib><creatorcontrib>Goud Langadi, Saya</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ghotgalkar, Shailesh Ganapat</au><au>Suvarna, Rajeev</au><au>Viswanathan Pillai, Prasanth</au><au>Goud Langadi, Saya</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Lockstep comparators and related methods</title><date>2024-07-02</date><risdate>2024</risdate><abstract>Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE TESTING |
| title | Lockstep comparators and related methods |
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