Optimizing use of computer resources in implementing circuit designs through machine learning
Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit desig...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Dehkordi, Mehrdad Eslami Kundarewich, Paul Tripathi, Vishal P, Karthic Yang, Xiaojian Kalase, Meghraj Pandya, Amish Sivaswamy, Satish Dasasathyan, Srinivasan |
| description | Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US12019964B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US12019964B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US12019964B13</originalsourceid><addsrcrecordid>eNqNyrEKwjAQBuAuDqK-w_kAglURulYUNwd1lBLi3-aguYRcsvj0KvgATt_yTavHJWb2_GIZqCgo9GSDjyUjUYKGkiyUWIh9HOEh-TstJ1s40xPKgyhll0IZHHljHQtohEnyifNq0ptRsfg5q5an4-1wXiGGDhqNhSB392u9WddNs9-19faf8wZ7aT1S</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Optimizing use of computer resources in implementing circuit designs through machine learning</title><source>esp@cenet</source><creator>Dehkordi, Mehrdad Eslami ; Kundarewich, Paul ; Tripathi, Vishal ; P, Karthic ; Yang, Xiaojian ; Kalase, Meghraj ; Pandya, Amish ; Sivaswamy, Satish ; Dasasathyan, Srinivasan</creator><creatorcontrib>Dehkordi, Mehrdad Eslami ; Kundarewich, Paul ; Tripathi, Vishal ; P, Karthic ; Yang, Xiaojian ; Kalase, Meghraj ; Pandya, Amish ; Sivaswamy, Satish ; Dasasathyan, Srinivasan</creatorcontrib><description>Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.</description><language>eng</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240625&DB=EPODOC&CC=US&NR=12019964B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240625&DB=EPODOC&CC=US&NR=12019964B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Dehkordi, Mehrdad Eslami</creatorcontrib><creatorcontrib>Kundarewich, Paul</creatorcontrib><creatorcontrib>Tripathi, Vishal</creatorcontrib><creatorcontrib>P, Karthic</creatorcontrib><creatorcontrib>Yang, Xiaojian</creatorcontrib><creatorcontrib>Kalase, Meghraj</creatorcontrib><creatorcontrib>Pandya, Amish</creatorcontrib><creatorcontrib>Sivaswamy, Satish</creatorcontrib><creatorcontrib>Dasasathyan, Srinivasan</creatorcontrib><title>Optimizing use of computer resources in implementing circuit designs through machine learning</title><description>Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQBuAuDqK-w_kAglURulYUNwd1lBLi3-aguYRcsvj0KvgATt_yTavHJWb2_GIZqCgo9GSDjyUjUYKGkiyUWIh9HOEh-TstJ1s40xPKgyhll0IZHHljHQtohEnyifNq0ptRsfg5q5an4-1wXiGGDhqNhSB392u9WddNs9-19faf8wZ7aT1S</recordid><startdate>20240625</startdate><enddate>20240625</enddate><creator>Dehkordi, Mehrdad Eslami</creator><creator>Kundarewich, Paul</creator><creator>Tripathi, Vishal</creator><creator>P, Karthic</creator><creator>Yang, Xiaojian</creator><creator>Kalase, Meghraj</creator><creator>Pandya, Amish</creator><creator>Sivaswamy, Satish</creator><creator>Dasasathyan, Srinivasan</creator><scope>EVB</scope></search><sort><creationdate>20240625</creationdate><title>Optimizing use of computer resources in implementing circuit designs through machine learning</title><author>Dehkordi, Mehrdad Eslami ; Kundarewich, Paul ; Tripathi, Vishal ; P, Karthic ; Yang, Xiaojian ; Kalase, Meghraj ; Pandya, Amish ; Sivaswamy, Satish ; Dasasathyan, Srinivasan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US12019964B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Dehkordi, Mehrdad Eslami</creatorcontrib><creatorcontrib>Kundarewich, Paul</creatorcontrib><creatorcontrib>Tripathi, Vishal</creatorcontrib><creatorcontrib>P, Karthic</creatorcontrib><creatorcontrib>Yang, Xiaojian</creatorcontrib><creatorcontrib>Kalase, Meghraj</creatorcontrib><creatorcontrib>Pandya, Amish</creatorcontrib><creatorcontrib>Sivaswamy, Satish</creatorcontrib><creatorcontrib>Dasasathyan, Srinivasan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dehkordi, Mehrdad Eslami</au><au>Kundarewich, Paul</au><au>Tripathi, Vishal</au><au>P, Karthic</au><au>Yang, Xiaojian</au><au>Kalase, Meghraj</au><au>Pandya, Amish</au><au>Sivaswamy, Satish</au><au>Dasasathyan, Srinivasan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Optimizing use of computer resources in implementing circuit designs through machine learning</title><date>2024-06-25</date><risdate>2024</risdate><abstract>Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US12019964B1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Optimizing use of computer resources in implementing circuit designs through machine learning |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T05%3A55%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Dehkordi,%20Mehrdad%20Eslami&rft.date=2024-06-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS12019964B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |