CMOS over array of 3-D DRAM device

Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers....

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Hauptverfasser: Fishburn, Fred, Varghese, Sony
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Varghese, Sony
description Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11980021B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11980021B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11980021B23</originalsourceid><addsrcrecordid>eNrjZFBy9vUPVsgvSy1SSCwqSqxUyE9TMNZ1UXAJcvRVSEkty0xO5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhoaWFgYGRoZORsbEqAEA1XYkAw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CMOS over array of 3-D DRAM device</title><source>esp@cenet</source><creator>Fishburn, Fred ; Varghese, Sony</creator><creatorcontrib>Fishburn, Fred ; Varghese, Sony</creatorcontrib><description>Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.</description><language>eng</language><subject>ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240507&amp;DB=EPODOC&amp;CC=US&amp;NR=11980021B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240507&amp;DB=EPODOC&amp;CC=US&amp;NR=11980021B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Fishburn, Fred</creatorcontrib><creatorcontrib>Varghese, Sony</creatorcontrib><title>CMOS over array of 3-D DRAM device</title><description>Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBy9vUPVsgvSy1SSCwqSqxUyE9TMNZ1UXAJcvRVSEkty0xO5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhoaWFgYGRoZORsbEqAEA1XYkAw</recordid><startdate>20240507</startdate><enddate>20240507</enddate><creator>Fishburn, Fred</creator><creator>Varghese, Sony</creator><scope>EVB</scope></search><sort><creationdate>20240507</creationdate><title>CMOS over array of 3-D DRAM device</title><author>Fishburn, Fred ; Varghese, Sony</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11980021B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>Fishburn, Fred</creatorcontrib><creatorcontrib>Varghese, Sony</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fishburn, Fred</au><au>Varghese, Sony</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CMOS over array of 3-D DRAM device</title><date>2024-05-07</date><risdate>2024</risdate><abstract>Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.</abstract><oa>free_for_read</oa></addata></record>
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title CMOS over array of 3-D DRAM device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T08%3A43%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Fishburn,%20Fred&rft.date=2024-05-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11980021B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true