Method for detecting stochastic weak points of layout pattern of semiconductor integrated circuit and computer system performing the same

A method for detecting a stochastic weak point of a layout pattern of a semiconductor integrated circuit includes: forming a semiconductor integrated circuit by exposing a wafer which is masked by a layout pattern and coated with a photoresist to light, and etching the circuit according to the layou...

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Bibliographische Detailangaben
Hauptverfasser: Choi, Dawoon, Koo, Kyoil, Lee, Seungjin, Song, Yunkyoung
Format: Patent
Sprache:eng
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