Interconnections for modular die designs

Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabil...

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Hauptverfasser: Avoinne, Christophe, Kamdar, Siddharth, Shah, Manav, Arya, Sanjay Jaisingh
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creator Avoinne, Christophe
Kamdar, Siddharth
Shah, Manav
Arya, Sanjay Jaisingh
description Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11972189B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11972189B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11972189B23</originalsourceid><addsrcrecordid>eNrjZNDwzCtJLUrOz8tLTS7JzM8rVkjLL1LIzU8pzUksUkjJTFVISS3OTM8r5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhoaW5kaGFpZORsbEqAEA-UIozg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Interconnections for modular die designs</title><source>esp@cenet</source><creator>Avoinne, Christophe ; Kamdar, Siddharth ; Shah, Manav ; Arya, Sanjay Jaisingh</creator><creatorcontrib>Avoinne, Christophe ; Kamdar, Siddharth ; Shah, Manav ; Arya, Sanjay Jaisingh</creatorcontrib><description>Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240430&amp;DB=EPODOC&amp;CC=US&amp;NR=11972189B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240430&amp;DB=EPODOC&amp;CC=US&amp;NR=11972189B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Avoinne, Christophe</creatorcontrib><creatorcontrib>Kamdar, Siddharth</creatorcontrib><creatorcontrib>Shah, Manav</creatorcontrib><creatorcontrib>Arya, Sanjay Jaisingh</creatorcontrib><title>Interconnections for modular die designs</title><description>Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDwzCtJLUrOz8tLTS7JzM8rVkjLL1LIzU8pzUksUkjJTFVISS3OTM8r5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhoaW5kaGFpZORsbEqAEA-UIozg</recordid><startdate>20240430</startdate><enddate>20240430</enddate><creator>Avoinne, Christophe</creator><creator>Kamdar, Siddharth</creator><creator>Shah, Manav</creator><creator>Arya, Sanjay Jaisingh</creator><scope>EVB</scope></search><sort><creationdate>20240430</creationdate><title>Interconnections for modular die designs</title><author>Avoinne, Christophe ; Kamdar, Siddharth ; Shah, Manav ; Arya, Sanjay Jaisingh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11972189B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Avoinne, Christophe</creatorcontrib><creatorcontrib>Kamdar, Siddharth</creatorcontrib><creatorcontrib>Shah, Manav</creatorcontrib><creatorcontrib>Arya, Sanjay Jaisingh</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Avoinne, Christophe</au><au>Kamdar, Siddharth</au><au>Shah, Manav</au><au>Arya, Sanjay Jaisingh</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Interconnections for modular die designs</title><date>2024-04-30</date><risdate>2024</risdate><abstract>Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
title Interconnections for modular die designs
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T16%3A11%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Avoinne,%20Christophe&rft.date=2024-04-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11972189B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true