Wafer stacking structure and manufacturing method thereof

A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer....

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Lu, Chun-Lin, Lin, Jium-Ming, Chang, Shou-Zen
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Lu, Chun-Lin
Lin, Jium-Ming
Chang, Shou-Zen
description A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11967558B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11967558B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11967558B23</originalsourceid><addsrcrecordid>eNrjZLAMT0xLLVIoLklMzs7MSwcyikqTS0qLUhUS81IUchPzStMSQXyQXG5qSUZ-ikJJRmpRan4aDwNrWmJOcSovlOZmUHRzDXH20E0tyI9PLS5ITE7NSy2JDw02NLQ0Mzc1tXAyMiZGDQCDAy93</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Wafer stacking structure and manufacturing method thereof</title><source>esp@cenet</source><creator>Lu, Chun-Lin ; Lin, Jium-Ming ; Chang, Shou-Zen</creator><creatorcontrib>Lu, Chun-Lin ; Lin, Jium-Ming ; Chang, Shou-Zen</creatorcontrib><description>A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.</description><language>eng</language><subject>ANTENNAS, i.e. RADIO AERIALS ; BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240423&amp;DB=EPODOC&amp;CC=US&amp;NR=11967558B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240423&amp;DB=EPODOC&amp;CC=US&amp;NR=11967558B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lu, Chun-Lin</creatorcontrib><creatorcontrib>Lin, Jium-Ming</creatorcontrib><creatorcontrib>Chang, Shou-Zen</creatorcontrib><title>Wafer stacking structure and manufacturing method thereof</title><description>A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.</description><subject>ANTENNAS, i.e. RADIO AERIALS</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAMT0xLLVIoLklMzs7MSwcyikqTS0qLUhUS81IUchPzStMSQXyQXG5qSUZ-ikJJRmpRan4aDwNrWmJOcSovlOZmUHRzDXH20E0tyI9PLS5ITE7NSy2JDw02NLQ0Mzc1tXAyMiZGDQCDAy93</recordid><startdate>20240423</startdate><enddate>20240423</enddate><creator>Lu, Chun-Lin</creator><creator>Lin, Jium-Ming</creator><creator>Chang, Shou-Zen</creator><scope>EVB</scope></search><sort><creationdate>20240423</creationdate><title>Wafer stacking structure and manufacturing method thereof</title><author>Lu, Chun-Lin ; Lin, Jium-Ming ; Chang, Shou-Zen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11967558B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>ANTENNAS, i.e. RADIO AERIALS</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lu, Chun-Lin</creatorcontrib><creatorcontrib>Lin, Jium-Ming</creatorcontrib><creatorcontrib>Chang, Shou-Zen</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lu, Chun-Lin</au><au>Lin, Jium-Ming</au><au>Chang, Shou-Zen</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wafer stacking structure and manufacturing method thereof</title><date>2024-04-23</date><risdate>2024</risdate><abstract>A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US11967558B2
source esp@cenet
subjects ANTENNAS, i.e. RADIO AERIALS
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Wafer stacking structure and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T20%3A59%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lu,%20Chun-Lin&rft.date=2024-04-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11967558B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true