Comparator circuit and ad converter
A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the ze...
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| creator | Fujimoto, Yoshiaki |
| description | A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11949418B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11949418B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11949418B23</originalsourceid><addsrcrecordid>eNrjZFB2zs8tSCxKLMkvUkjOLEouzSxRSMxLUUhMUUjOzytLLSpJLeJhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGliaWJoYWTkbGxKgBAOeDJqM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Comparator circuit and ad converter</title><source>esp@cenet</source><creator>Fujimoto, Yoshiaki</creator><creatorcontrib>Fujimoto, Yoshiaki</creatorcontrib><description>A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; DECODING ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240402&DB=EPODOC&CC=US&NR=11949418B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240402&DB=EPODOC&CC=US&NR=11949418B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Fujimoto, Yoshiaki</creatorcontrib><title>Comparator circuit and ad converter</title><description>A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB2zs8tSCxKLMkvUkjOLEouzSxRSMxLUUhMUUjOzytLLSpJLeJhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGliaWJoYWTkbGxKgBAOeDJqM</recordid><startdate>20240402</startdate><enddate>20240402</enddate><creator>Fujimoto, Yoshiaki</creator><scope>EVB</scope></search><sort><creationdate>20240402</creationdate><title>Comparator circuit and ad converter</title><author>Fujimoto, Yoshiaki</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11949418B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>Fujimoto, Yoshiaki</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fujimoto, Yoshiaki</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Comparator circuit and ad converter</title><date>2024-04-02</date><risdate>2024</risdate><abstract>A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY PULSE TECHNIQUE |
| title | Comparator circuit and ad converter |
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