Dielectric protection layer in middle-of-line interconnect structure manufacturing method

In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower...

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Bibliographische Detailangaben

Hauptverfasser:	Liu, Hao-Heng, Huang, Kuan-Da, Lin, Li-Te
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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