Lossless tiling in convolution networks-backward pass

Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative in...

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Hauptverfasser: Chaphekar, Ruddhi, Sivaramakrishnan, Ram, Musaddiq, Matheen, Prabhakar, Raghu, Fuchs, Adi, Wang, Junjue, Sujeeth, Arvind Krishna, Jairath, Sumti, Nama, Tejas Nagendra Babu, Liang, Kaizhao
Format: Patent
Sprache:eng
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Zusammenfassung:Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.