Dielectric isolation layer between a nanowire transistor and a substrate

Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-k") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Guler, Leonard, Kang, Jun Sung, Beattie, Bruce E, Guha, Biswajeet, Hsu, William
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Guler, Leonard Kang, Jun Sung Beattie, Bruce E Guha, Biswajeet Hsu, William
description	Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-k") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11901458B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11901458B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11901458B23</originalsourceid><addsrcrecordid>eNqNiksKwkAQBbNxIeod2gMIjh_QrT-yV9ehM75Aw9ATpluCtzcLD-CqoKqmVX0RJEQvEkksJ3bJSok_KNTCB0CJSVnzIAXkhdXEPBdifY3F3q2N0jGvJh0nw-LHWbW8XR_neoU-N7CeIxTePO8hHNdhtz-cNtt_ni_bVjTc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dielectric isolation layer between a nanowire transistor and a substrate</title><source>esp@cenet</source><creator>Guler, Leonard ; Kang, Jun Sung ; Beattie, Bruce E ; Guha, Biswajeet ; Hsu, William</creator><creatorcontrib>Guler, Leonard ; Kang, Jun Sung ; Beattie, Bruce E ; Guha, Biswajeet ; Hsu, William</creatorcontrib><description>Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-k") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240213&DB=EPODOC&CC=US&NR=11901458B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240213&DB=EPODOC&CC=US&NR=11901458B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Guler, Leonard</creatorcontrib><creatorcontrib>Kang, Jun Sung</creatorcontrib><creatorcontrib>Beattie, Bruce E</creatorcontrib><creatorcontrib>Guha, Biswajeet</creatorcontrib><creatorcontrib>Hsu, William</creatorcontrib><title>Dielectric isolation layer between a nanowire transistor and a substrate</title><description>Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-k") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNiksKwkAQBbNxIeod2gMIjh_QrT-yV9ehM75Aw9ATpluCtzcLD-CqoKqmVX0RJEQvEkksJ3bJSok_KNTCB0CJSVnzIAXkhdXEPBdifY3F3q2N0jGvJh0nw-LHWbW8XR_neoU-N7CeIxTePO8hHNdhtz-cNtt_ni_bVjTc</recordid><startdate>20240213</startdate><enddate>20240213</enddate><creator>Guler, Leonard</creator><creator>Kang, Jun Sung</creator><creator>Beattie, Bruce E</creator><creator>Guha, Biswajeet</creator><creator>Hsu, William</creator><scope>EVB</scope></search><sort><creationdate>20240213</creationdate><title>Dielectric isolation layer between a nanowire transistor and a substrate</title><author>Guler, Leonard ; Kang, Jun Sung ; Beattie, Bruce E ; Guha, Biswajeet ; Hsu, William</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11901458B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Guler, Leonard</creatorcontrib><creatorcontrib>Kang, Jun Sung</creatorcontrib><creatorcontrib>Beattie, Bruce E</creatorcontrib><creatorcontrib>Guha, Biswajeet</creatorcontrib><creatorcontrib>Hsu, William</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Guler, Leonard</au><au>Kang, Jun Sung</au><au>Beattie, Bruce E</au><au>Guha, Biswajeet</au><au>Hsu, William</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dielectric isolation layer between a nanowire transistor and a substrate</title><date>2024-02-13</date><risdate>2024</risdate><abstract>Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-k") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US11901458B2
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Dielectric isolation layer between a nanowire transistor and a substrate
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T00%3A23%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Guler,%20Leonard&rft.date=2024-02-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11901458B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true