Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions

A compiler generates a computer program implementing a machine learning network on a machine learning accelerator (MLA) including interconnected processing elements. The computer program includes data transfer instructions for non-colliding data transfers between the processing elements. To generate...

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Hauptverfasser:	Shah, Nishit, Dhruvanarayan, Srivathsa, Kotler, Reed
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING PHYSICS
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creator	Shah, Nishit Dhruvanarayan, Srivathsa Kotler, Reed
description	A compiler generates a computer program implementing a machine learning network on a machine learning accelerator (MLA) including interconnected processing elements. The computer program includes data transfer instructions for non-colliding data transfers between the processing elements. To generate the data transfer instructions, the compiler determines non-conflicting data transfer paths for data transfers based on a topology of the interconnections between processing elements, on dependencies of the instructions and on a duration for execution of the instructions. Each data transfer path specifies a routing and a time slot for the data transfer. The compiler generates data transfer instructions that specify routing of the data transfers and generates a static schedule that schedules execution of the data transfer instructions during the time slots for the data transfers. The static schedule also schedules execution of compute instructions for computations using transferred data that implement the machine learning network.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11886981B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11886981B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11886981B23</originalsourceid><addsrcrecordid>eNqNi7EKwkAMQLs4iPoPcbfDKUhdFUVndS4hTb2DM1eSdPDvVfADnB483ptW8SLOWg9aiM2KQoeO4IpiPSskAYQnUkzCkBlVkjwAiTizohddwWhfZY6eCHN-gVHkbszcfW5zHclTEZtXkx6z8eLHWbU8HW-Hc81DadkGJBb29n4NoWm2uybs15t_mjdV50FZ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions</title><source>esp@cenet</source><creator>Shah, Nishit ; Dhruvanarayan, Srivathsa ; Kotler, Reed</creator><creatorcontrib>Shah, Nishit ; Dhruvanarayan, Srivathsa ; Kotler, Reed</creatorcontrib><description>A compiler generates a computer program implementing a machine learning network on a machine learning accelerator (MLA) including interconnected processing elements. The computer program includes data transfer instructions for non-colliding data transfers between the processing elements. To generate the data transfer instructions, the compiler determines non-conflicting data transfer paths for data transfers based on a topology of the interconnections between processing elements, on dependencies of the instructions and on a duration for execution of the instructions. Each data transfer path specifies a routing and a time slot for the data transfer. The compiler generates data transfer instructions that specify routing of the data transfers and generates a static schedule that schedules execution of the data transfer instructions during the time slots for the data transfers. The static schedule also schedules execution of compute instructions for computations using transferred data that implement the machine learning network.</description><language>eng</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240130&DB=EPODOC&CC=US&NR=11886981B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240130&DB=EPODOC&CC=US&NR=11886981B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Shah, Nishit</creatorcontrib><creatorcontrib>Dhruvanarayan, Srivathsa</creatorcontrib><creatorcontrib>Kotler, Reed</creatorcontrib><title>Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions</title><description>A compiler generates a computer program implementing a machine learning network on a machine learning accelerator (MLA) including interconnected processing elements. The computer program includes data transfer instructions for non-colliding data transfers between the processing elements. To generate the data transfer instructions, the compiler determines non-conflicting data transfer paths for data transfers based on a topology of the interconnections between processing elements, on dependencies of the instructions and on a duration for execution of the instructions. Each data transfer path specifies a routing and a time slot for the data transfer. The compiler generates data transfer instructions that specify routing of the data transfers and generates a static schedule that schedules execution of the data transfer instructions during the time slots for the data transfers. The static schedule also schedules execution of compute instructions for computations using transferred data that implement the machine learning network.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwkAMQLs4iPoPcbfDKUhdFUVndS4hTb2DM1eSdPDvVfADnB483ptW8SLOWg9aiM2KQoeO4IpiPSskAYQnUkzCkBlVkjwAiTizohddwWhfZY6eCHN-gVHkbszcfW5zHclTEZtXkx6z8eLHWbU8HW-Hc81DadkGJBb29n4NoWm2uybs15t_mjdV50FZ</recordid><startdate>20240130</startdate><enddate>20240130</enddate><creator>Shah, Nishit</creator><creator>Dhruvanarayan, Srivathsa</creator><creator>Kotler, Reed</creator><scope>EVB</scope></search><sort><creationdate>20240130</creationdate><title>Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions</title><author>Shah, Nishit ; Dhruvanarayan, Srivathsa ; Kotler, Reed</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11886981B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Shah, Nishit</creatorcontrib><creatorcontrib>Dhruvanarayan, Srivathsa</creatorcontrib><creatorcontrib>Kotler, Reed</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shah, Nishit</au><au>Dhruvanarayan, Srivathsa</au><au>Kotler, Reed</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions</title><date>2024-01-30</date><risdate>2024</risdate><abstract>A compiler generates a computer program implementing a machine learning network on a machine learning accelerator (MLA) including interconnected processing elements. The computer program includes data transfer instructions for non-colliding data transfers between the processing elements. To generate the data transfer instructions, the compiler determines non-conflicting data transfer paths for data transfers based on a topology of the interconnections between processing elements, on dependencies of the instructions and on a duration for execution of the instructions. Each data transfer path specifies a routing and a time slot for the data transfer. The compiler generates data transfer instructions that specify routing of the data transfers and generates a static schedule that schedules execution of the data transfer instructions during the time slots for the data transfers. The static schedule also schedules execution of compute instructions for computations using transferred data that implement the machine learning network.</abstract><oa>free_for_read</oa></addata></record>
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title	Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T12%3A58%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Shah,%20Nishit&rft.date=2024-01-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11886981B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true