Variable tick for DRAM interface calibration
Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the tra...
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creator | Eaton, Craig Daniel Ashtiani, Pouya Najafi Kashem, Anwar |
description | Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM. |
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Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240116&DB=EPODOC&CC=US&NR=11875875B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240116&DB=EPODOC&CC=US&NR=11875875B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Eaton, Craig Daniel</creatorcontrib><creatorcontrib>Ashtiani, Pouya Najafi</creatorcontrib><creatorcontrib>Kashem, Anwar</creatorcontrib><title>Variable tick for DRAM interface calibration</title><description>Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAJSyzKTEzKSVUoyUzOVkjLL1JwCXL0VcjMK0ktSktMTlVITszJTCpKLMnMz-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBUDleakl8aHBhoYW5qZA5GRkTIwaAFD3KXA</recordid><startdate>20240116</startdate><enddate>20240116</enddate><creator>Eaton, Craig Daniel</creator><creator>Ashtiani, Pouya Najafi</creator><creator>Kashem, Anwar</creator><scope>EVB</scope></search><sort><creationdate>20240116</creationdate><title>Variable tick for DRAM interface calibration</title><author>Eaton, Craig Daniel ; Ashtiani, Pouya Najafi ; Kashem, Anwar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11875875B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Eaton, Craig Daniel</creatorcontrib><creatorcontrib>Ashtiani, Pouya Najafi</creatorcontrib><creatorcontrib>Kashem, Anwar</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Eaton, Craig Daniel</au><au>Ashtiani, Pouya Najafi</au><au>Kashem, Anwar</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Variable tick for DRAM interface calibration</title><date>2024-01-16</date><risdate>2024</risdate><abstract>Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.</abstract><oa>free_for_read</oa></addata></record> |
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title | Variable tick for DRAM interface calibration |
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