Cache memory error analysis and management thereof

A system includes an obsolete cache-line vector having a plurality of memory elements, wherein each memory element has a one-to-one correspondence to a cache line entry of a cache memory. The vector can capture cache line errors that occur at different times from an error detection logic associated...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Habusha, Adi, Naaman, Ofer, Katz, Osnat, Bar-Or, Nir
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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