Configuration latch for programmable logic device

An area efficient readable and resettable configuration memory latch is disclosed that maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL d...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yap, Ket Chong, Liao, Chihhung
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES
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