Executing a neural network graph using a non-homogenous set of reconfigurable processors

A system for executing a graph partitioned across a plurality of reconfigurable computing units includes a processing node that has a first computing unit reconfigurable at a first level of configuration granularity and a second computing unit reconfigurable at a second, finer, level of configuratio...

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Hauptverfasser: Kumar, Ravinder, Leung, Kin Hing, Grohoski, Gregory Frederick, Shah, Bandish B, Raumann, Martin Russell, Jairath, Sumti, Zheng, Qi
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creator Kumar, Ravinder
Leung, Kin Hing
Grohoski, Gregory Frederick
Shah, Bandish B
Raumann, Martin Russell
Jairath, Sumti
Zheng, Qi
description A system for executing a graph partitioned across a plurality of reconfigurable computing units includes a processing node that has a first computing unit reconfigurable at a first level of configuration granularity and a second computing unit reconfigurable at a second, finer, level of configuration granularity. The first computing unit is configured by a host system to execute a first dataflow segment of the graph using one or more dataflow pipelines to generate a first intermediate result and to provide the first intermediate result to the second computing unit without passing through the host system. The second computing unit is configured by the host system to execute a second dataflow segment of the graph, dependent upon the first intermediate result, to generate a second intermediate result and to send the second intermediate result to a third computing unit, without passing through the host system, to continue execution of the graph.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11847395B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11847395B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11847395B23</originalsourceid><addsrcrecordid>eNqNjTEOwjAQBN1QIOAPxwNShIAILSiIHpDoImOdnQjjs-5swfNxkQdQTbGzmrl6dF80OY3BgYaAmbUvSB_iFzjWcYAs00ihGuhNDgNlAcEEZIHRULCjK8enR4hMBkWIZalmVnvB1cSFWp-72-lSYaQeJWqDpdPfr3XdbvfNYXfcNP84P9epOw4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Executing a neural network graph using a non-homogenous set of reconfigurable processors</title><source>esp@cenet</source><creator>Kumar, Ravinder ; Leung, Kin Hing ; Grohoski, Gregory Frederick ; Shah, Bandish B ; Raumann, Martin Russell ; Jairath, Sumti ; Zheng, Qi</creator><creatorcontrib>Kumar, Ravinder ; Leung, Kin Hing ; Grohoski, Gregory Frederick ; Shah, Bandish B ; Raumann, Martin Russell ; Jairath, Sumti ; Zheng, Qi</creatorcontrib><description>A system for executing a graph partitioned across a plurality of reconfigurable computing units includes a processing node that has a first computing unit reconfigurable at a first level of configuration granularity and a second computing unit reconfigurable at a second, finer, level of configuration granularity. The first computing unit is configured by a host system to execute a first dataflow segment of the graph using one or more dataflow pipelines to generate a first intermediate result and to provide the first intermediate result to the second computing unit without passing through the host system. The second computing unit is configured by the host system to execute a second dataflow segment of the graph, dependent upon the first intermediate result, to generate a second intermediate result and to send the second intermediate result to a third computing unit, without passing through the host system, to continue execution of the graph.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231219&amp;DB=EPODOC&amp;CC=US&amp;NR=11847395B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231219&amp;DB=EPODOC&amp;CC=US&amp;NR=11847395B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kumar, Ravinder</creatorcontrib><creatorcontrib>Leung, Kin Hing</creatorcontrib><creatorcontrib>Grohoski, Gregory Frederick</creatorcontrib><creatorcontrib>Shah, Bandish B</creatorcontrib><creatorcontrib>Raumann, Martin Russell</creatorcontrib><creatorcontrib>Jairath, Sumti</creatorcontrib><creatorcontrib>Zheng, Qi</creatorcontrib><title>Executing a neural network graph using a non-homogenous set of reconfigurable processors</title><description>A system for executing a graph partitioned across a plurality of reconfigurable computing units includes a processing node that has a first computing unit reconfigurable at a first level of configuration granularity and a second computing unit reconfigurable at a second, finer, level of configuration granularity. The first computing unit is configured by a host system to execute a first dataflow segment of the graph using one or more dataflow pipelines to generate a first intermediate result and to provide the first intermediate result to the second computing unit without passing through the host system. The second computing unit is configured by the host system to execute a second dataflow segment of the graph, dependent upon the first intermediate result, to generate a second intermediate result and to send the second intermediate result to a third computing unit, without passing through the host system, to continue execution of the graph.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjTEOwjAQBN1QIOAPxwNShIAILSiIHpDoImOdnQjjs-5swfNxkQdQTbGzmrl6dF80OY3BgYaAmbUvSB_iFzjWcYAs00ihGuhNDgNlAcEEZIHRULCjK8enR4hMBkWIZalmVnvB1cSFWp-72-lSYaQeJWqDpdPfr3XdbvfNYXfcNP84P9epOw4</recordid><startdate>20231219</startdate><enddate>20231219</enddate><creator>Kumar, Ravinder</creator><creator>Leung, Kin Hing</creator><creator>Grohoski, Gregory Frederick</creator><creator>Shah, Bandish B</creator><creator>Raumann, Martin Russell</creator><creator>Jairath, Sumti</creator><creator>Zheng, Qi</creator><scope>EVB</scope></search><sort><creationdate>20231219</creationdate><title>Executing a neural network graph using a non-homogenous set of reconfigurable processors</title><author>Kumar, Ravinder ; Leung, Kin Hing ; Grohoski, Gregory Frederick ; Shah, Bandish B ; Raumann, Martin Russell ; Jairath, Sumti ; Zheng, Qi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11847395B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Kumar, Ravinder</creatorcontrib><creatorcontrib>Leung, Kin Hing</creatorcontrib><creatorcontrib>Grohoski, Gregory Frederick</creatorcontrib><creatorcontrib>Shah, Bandish B</creatorcontrib><creatorcontrib>Raumann, Martin Russell</creatorcontrib><creatorcontrib>Jairath, Sumti</creatorcontrib><creatorcontrib>Zheng, Qi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kumar, Ravinder</au><au>Leung, Kin Hing</au><au>Grohoski, Gregory Frederick</au><au>Shah, Bandish B</au><au>Raumann, Martin Russell</au><au>Jairath, Sumti</au><au>Zheng, Qi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Executing a neural network graph using a non-homogenous set of reconfigurable processors</title><date>2023-12-19</date><risdate>2023</risdate><abstract>A system for executing a graph partitioned across a plurality of reconfigurable computing units includes a processing node that has a first computing unit reconfigurable at a first level of configuration granularity and a second computing unit reconfigurable at a second, finer, level of configuration granularity. The first computing unit is configured by a host system to execute a first dataflow segment of the graph using one or more dataflow pipelines to generate a first intermediate result and to provide the first intermediate result to the second computing unit without passing through the host system. The second computing unit is configured by the host system to execute a second dataflow segment of the graph, dependent upon the first intermediate result, to generate a second intermediate result and to send the second intermediate result to a third computing unit, without passing through the host system, to continue execution of the graph.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Executing a neural network graph using a non-homogenous set of reconfigurable processors
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T20%3A58%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kumar,%20Ravinder&rft.date=2023-12-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11847395B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true