Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

Disclosed embodiments relate to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non...

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Bibliographische Detailangaben

Hauptverfasser:	Heinecke, Alexander F, Baum, Dan, Ould-Ahmed-Vall, Elmoustapha, Koren, Chen, Hughes, Christopher J, Sade, Raanan, Charney, Mark J, Valentine, Robert, Espig, Michael
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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