Vector-scalar logical clock and associated method, apparatus and system

A logical clock is implemented in networked nodes. Messages between nodes can include either a scalar timestamp or a vector timestamp. The scalar timestamp leads to an overhead reduction, and nodes can select whether to send a scalar or vector timestamp depending on requirements. Message recipients...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Larson, Per-Ake, Chen, Chong, Ng, Jack Hon Wai, Depoutovitch, Alexandre
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Larson, Per-Ake
Chen, Chong
Ng, Jack Hon Wai
Depoutovitch, Alexandre
description A logical clock is implemented in networked nodes. Messages between nodes can include either a scalar timestamp or a vector timestamp. The scalar timestamp leads to an overhead reduction, and nodes can select whether to send a scalar or vector timestamp depending on requirements. Message recipients update their logical clock vector differently depending on whether the scalar or vector timestamp is received. Applications to multi-master databases are also provided. The clock conforms to Lamport clock requirements when the scalar timestamp is sent, and conforms to both Lamport and vector clock requirements when the vector timestamp is sent.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11843663B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11843663B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11843663B13</originalsourceid><addsrcrecordid>eNrjZHAPS00uyS_SLU5OzEksUsjJT88EshSSc_KTsxUS81IUEouL85MzE0tSUxRyU0sy8lN0FBILChKLEktKi8EKiiuLS1JzeRhY0xJzilN5oTQ3g6Kba4izh25qQX58anFBYnJqXmpJfGiwoaGFibGZmbGToTExagBgVjQG</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Vector-scalar logical clock and associated method, apparatus and system</title><source>esp@cenet</source><creator>Larson, Per-Ake ; Chen, Chong ; Ng, Jack Hon Wai ; Depoutovitch, Alexandre</creator><creatorcontrib>Larson, Per-Ake ; Chen, Chong ; Ng, Jack Hon Wai ; Depoutovitch, Alexandre</creatorcontrib><description>A logical clock is implemented in networked nodes. Messages between nodes can include either a scalar timestamp or a vector timestamp. The scalar timestamp leads to an overhead reduction, and nodes can select whether to send a scalar or vector timestamp depending on requirements. Message recipients update their logical clock vector differently depending on whether the scalar or vector timestamp is received. Applications to multi-master databases are also provided. The clock conforms to Lamport clock requirements when the scalar timestamp is sent, and conforms to both Lamport and vector clock requirements when the vector timestamp is sent.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231212&amp;DB=EPODOC&amp;CC=US&amp;NR=11843663B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231212&amp;DB=EPODOC&amp;CC=US&amp;NR=11843663B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Larson, Per-Ake</creatorcontrib><creatorcontrib>Chen, Chong</creatorcontrib><creatorcontrib>Ng, Jack Hon Wai</creatorcontrib><creatorcontrib>Depoutovitch, Alexandre</creatorcontrib><title>Vector-scalar logical clock and associated method, apparatus and system</title><description>A logical clock is implemented in networked nodes. Messages between nodes can include either a scalar timestamp or a vector timestamp. The scalar timestamp leads to an overhead reduction, and nodes can select whether to send a scalar or vector timestamp depending on requirements. Message recipients update their logical clock vector differently depending on whether the scalar or vector timestamp is received. Applications to multi-master databases are also provided. The clock conforms to Lamport clock requirements when the scalar timestamp is sent, and conforms to both Lamport and vector clock requirements when the vector timestamp is sent.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAPS00uyS_SLU5OzEksUsjJT88EshSSc_KTsxUS81IUEouL85MzE0tSUxRyU0sy8lN0FBILChKLEktKi8EKiiuLS1JzeRhY0xJzilN5oTQ3g6Kba4izh25qQX58anFBYnJqXmpJfGiwoaGFibGZmbGToTExagBgVjQG</recordid><startdate>20231212</startdate><enddate>20231212</enddate><creator>Larson, Per-Ake</creator><creator>Chen, Chong</creator><creator>Ng, Jack Hon Wai</creator><creator>Depoutovitch, Alexandre</creator><scope>EVB</scope></search><sort><creationdate>20231212</creationdate><title>Vector-scalar logical clock and associated method, apparatus and system</title><author>Larson, Per-Ake ; Chen, Chong ; Ng, Jack Hon Wai ; Depoutovitch, Alexandre</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11843663B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Larson, Per-Ake</creatorcontrib><creatorcontrib>Chen, Chong</creatorcontrib><creatorcontrib>Ng, Jack Hon Wai</creatorcontrib><creatorcontrib>Depoutovitch, Alexandre</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Larson, Per-Ake</au><au>Chen, Chong</au><au>Ng, Jack Hon Wai</au><au>Depoutovitch, Alexandre</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Vector-scalar logical clock and associated method, apparatus and system</title><date>2023-12-12</date><risdate>2023</risdate><abstract>A logical clock is implemented in networked nodes. Messages between nodes can include either a scalar timestamp or a vector timestamp. The scalar timestamp leads to an overhead reduction, and nodes can select whether to send a scalar or vector timestamp depending on requirements. Message recipients update their logical clock vector differently depending on whether the scalar or vector timestamp is received. Applications to multi-master databases are also provided. The clock conforms to Lamport clock requirements when the scalar timestamp is sent, and conforms to both Lamport and vector clock requirements when the vector timestamp is sent.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US11843663B1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Vector-scalar logical clock and associated method, apparatus and system
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T21%3A38%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Larson,%20Per-Ake&rft.date=2023-12-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11843663B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true