Hierarchical statistically multiplexed counters and a method thereof
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcou...
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| creator | Atluri, Srinath Schmidt, Gerald Ma, Weinan Lnu, Shrikant Sundaram Wang, Weihuang |
| description | Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life. |
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Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. 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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PULSE TECHNIQUE TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | Hierarchical statistically multiplexed counters and a method thereof |
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