Asynchronous interrupt event handling in multi-plane memory devices

A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchron...

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Bibliographische Detailangaben

Hauptverfasser:	Xotta, Andrea Giovanni, Vali, Tommaso, Siciliani, Umberto, Rizzo, Guido Luciano, De Santis, Luca, Di Francesco, Walter
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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