Chiplet gearbox for low-cost multi-chip module applications

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a first integrated circuit (IC) chip including a first interface defining a first number of interface contacts. Conversion circuitry receives a first full set of signals associated with the first interface and to omit a subset of the full set of signals to generate a reduced set of signals. Serialization circuitry serializes the reduced set of signals to generate a serialized set of signals. A second interface transmits the serialized set of signals with a second number of interface contacts that is less than the first number of interface contacts. A logic IC chip includes a third interface coupled to the second interface via a set of links and configured to match the second interface. Deserialization circuitry deserializes the serialized set of signals. Reconversion circuitry recreates signals corresponding to the omitted subset of the full set of signals and aggregates the recreated signals with the deserialized signals to form a second full set of signals that correspond to the first full set of signals.