Cell architecture with backside power rails

Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard ce...

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Hauptverfasser: Edathil, Sharath Koodali, Frederick, Jr., Marlin Wayne
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creator Edathil, Sharath Koodali
Frederick, Jr., Marlin Wayne
description Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11836432B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11836432B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11836432B23</originalsourceid><addsrcrecordid>eNrjZNB2Ts3JUUgsSs7ILElNLiktSlUozyzJUEhKTM4uzkxJVSjIL08tUihKzMwp5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhoYWxmYmxkZORsbEqAEAaXcpmw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Cell architecture with backside power rails</title><source>esp@cenet</source><creator>Edathil, Sharath Koodali ; Frederick, Jr., Marlin Wayne</creator><creatorcontrib>Edathil, Sharath Koodali ; Frederick, Jr., Marlin Wayne</creatorcontrib><description>Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231205&amp;DB=EPODOC&amp;CC=US&amp;NR=11836432B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231205&amp;DB=EPODOC&amp;CC=US&amp;NR=11836432B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Edathil, Sharath Koodali</creatorcontrib><creatorcontrib>Frederick, Jr., Marlin Wayne</creatorcontrib><title>Cell architecture with backside power rails</title><description>Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB2Ts3JUUgsSs7ILElNLiktSlUozyzJUEhKTM4uzkxJVSjIL08tUihKzMwp5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhoYWxmYmxkZORsbEqAEAaXcpmw</recordid><startdate>20231205</startdate><enddate>20231205</enddate><creator>Edathil, Sharath Koodali</creator><creator>Frederick, Jr., Marlin Wayne</creator><scope>EVB</scope></search><sort><creationdate>20231205</creationdate><title>Cell architecture with backside power rails</title><author>Edathil, Sharath Koodali ; Frederick, Jr., Marlin Wayne</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11836432B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Edathil, Sharath Koodali</creatorcontrib><creatorcontrib>Frederick, Jr., Marlin Wayne</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Edathil, Sharath Koodali</au><au>Frederick, Jr., Marlin Wayne</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cell architecture with backside power rails</title><date>2023-12-05</date><risdate>2023</risdate><abstract>Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Cell architecture with backside power rails
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T10%3A48%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Edathil,%20Sharath%20Koodali&rft.date=2023-12-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11836432B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true