Memory device and operation method thereof
A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data...
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| creator | Lee, Yung-Chun Wang, Huai-Mu Hu, Han-Wen Lin, Bo-Rong |
| description | A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11809838B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11809838B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11809838B23</originalsourceid><addsrcrecordid>eNrjZNDyTc3NL6pUSEkty0xOVUjMS1HIL0gtSizJzM9TyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhhYGlhbGFk5GxsSoAQA3pSlM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Memory device and operation method thereof</title><source>esp@cenet</source><creator>Lee, Yung-Chun ; Wang, Huai-Mu ; Hu, Han-Wen ; Lin, Bo-Rong</creator><creatorcontrib>Lee, Yung-Chun ; Wang, Huai-Mu ; Hu, Han-Wen ; Lin, Bo-Rong</creatorcontrib><description>A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231107&DB=EPODOC&CC=US&NR=11809838B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231107&DB=EPODOC&CC=US&NR=11809838B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lee, Yung-Chun</creatorcontrib><creatorcontrib>Wang, Huai-Mu</creatorcontrib><creatorcontrib>Hu, Han-Wen</creatorcontrib><creatorcontrib>Lin, Bo-Rong</creatorcontrib><title>Memory device and operation method thereof</title><description>A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDyTc3NL6pUSEkty0xOVUjMS1HIL0gtSizJzM9TyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhhYGlhbGFk5GxsSoAQA3pSlM</recordid><startdate>20231107</startdate><enddate>20231107</enddate><creator>Lee, Yung-Chun</creator><creator>Wang, Huai-Mu</creator><creator>Hu, Han-Wen</creator><creator>Lin, Bo-Rong</creator><scope>EVB</scope></search><sort><creationdate>20231107</creationdate><title>Memory device and operation method thereof</title><author>Lee, Yung-Chun ; Wang, Huai-Mu ; Hu, Han-Wen ; Lin, Bo-Rong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11809838B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, Yung-Chun</creatorcontrib><creatorcontrib>Wang, Huai-Mu</creatorcontrib><creatorcontrib>Hu, Han-Wen</creatorcontrib><creatorcontrib>Lin, Bo-Rong</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Yung-Chun</au><au>Wang, Huai-Mu</au><au>Hu, Han-Wen</au><au>Lin, Bo-Rong</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory device and operation method thereof</title><date>2023-11-07</date><risdate>2023</risdate><abstract>A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Memory device and operation method thereof |
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