Hardware accelerator for efficient convolution processing

An accelerator with a modified kernel design for convolution processing in a Convolutional Neural Network (CNN) model is disclosed wherein the convolution execution time is reduced. A kernel structure is disclosed in the embodiment for the convolution operations that improves the overall performance...

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Hauptverfasser:	Rahaman, Hafizur, Poddar, Soumyajit, Naidu, Prakash C R J, Hazarika, Anakhi
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS
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creator	Rahaman, Hafizur Poddar, Soumyajit Naidu, Prakash C R J Hazarika, Anakhi
description	An accelerator with a modified kernel design for convolution processing in a Convolutional Neural Network (CNN) model is disclosed wherein the convolution execution time is reduced. A kernel structure is disclosed in the embodiment for the convolution operations that improves the overall performance of a CNN. Further, two loading units for weight and pixel loading reduce the latency involved in loading the network parameters into the processing elements. Moreover, a controller has been designed and included in the system architecture to aid the functioning of loading units efficiently.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11797345B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11797345B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11797345B23</originalsourceid><addsrcrecordid>eNrjZLD0SCxKKU8sSlVITE5OzUktSizJL1JIA-LUtLTM5MzUvBKF5Py8svyc0pLM_DyFgqL85NTi4sy8dB4G1rTEnOJUXijNzaDo5hri7KGbWpAfn1pckJicmpdaEh8abGhobmlubGLqZGRMjBoAkkUvog</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Hardware accelerator for efficient convolution processing</title><source>esp@cenet</source><creator>Rahaman, Hafizur ; Poddar, Soumyajit ; Naidu, Prakash C R J ; Hazarika, Anakhi</creator><creatorcontrib>Rahaman, Hafizur ; Poddar, Soumyajit ; Naidu, Prakash C R J ; Hazarika, Anakhi</creatorcontrib><description>An accelerator with a modified kernel design for convolution processing in a Convolutional Neural Network (CNN) model is disclosed wherein the convolution execution time is reduced. A kernel structure is disclosed in the embodiment for the convolution operations that improves the overall performance of a CNN. Further, two loading units for weight and pixel loading reduce the latency involved in loading the network parameters into the processing elements. Moreover, a controller has been designed and included in the system architecture to aid the functioning of loading units efficiently.</description><language>eng</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231024&DB=EPODOC&CC=US&NR=11797345B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,782,887,25571,76555</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231024&DB=EPODOC&CC=US&NR=11797345B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Rahaman, Hafizur</creatorcontrib><creatorcontrib>Poddar, Soumyajit</creatorcontrib><creatorcontrib>Naidu, Prakash C R J</creatorcontrib><creatorcontrib>Hazarika, Anakhi</creatorcontrib><title>Hardware accelerator for efficient convolution processing</title><description>An accelerator with a modified kernel design for convolution processing in a Convolutional Neural Network (CNN) model is disclosed wherein the convolution execution time is reduced. A kernel structure is disclosed in the embodiment for the convolution operations that improves the overall performance of a CNN. Further, two loading units for weight and pixel loading reduce the latency involved in loading the network parameters into the processing elements. Moreover, a controller has been designed and included in the system architecture to aid the functioning of loading units efficiently.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD0SCxKKU8sSlVITE5OzUktSizJL1JIA-LUtLTM5MzUvBKF5Py8svyc0pLM_DyFgqL85NTi4sy8dB4G1rTEnOJUXijNzaDo5hri7KGbWpAfn1pckJicmpdaEh8abGhobmlubGLqZGRMjBoAkkUvog</recordid><startdate>20231024</startdate><enddate>20231024</enddate><creator>Rahaman, Hafizur</creator><creator>Poddar, Soumyajit</creator><creator>Naidu, Prakash C R J</creator><creator>Hazarika, Anakhi</creator><scope>EVB</scope></search><sort><creationdate>20231024</creationdate><title>Hardware accelerator for efficient convolution processing</title><author>Rahaman, Hafizur ; Poddar, Soumyajit ; Naidu, Prakash C R J ; Hazarika, Anakhi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11797345B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Rahaman, Hafizur</creatorcontrib><creatorcontrib>Poddar, Soumyajit</creatorcontrib><creatorcontrib>Naidu, Prakash C R J</creatorcontrib><creatorcontrib>Hazarika, Anakhi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rahaman, Hafizur</au><au>Poddar, Soumyajit</au><au>Naidu, Prakash C R J</au><au>Hazarika, Anakhi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Hardware accelerator for efficient convolution processing</title><date>2023-10-24</date><risdate>2023</risdate><abstract>An accelerator with a modified kernel design for convolution processing in a Convolutional Neural Network (CNN) model is disclosed wherein the convolution execution time is reduced. A kernel structure is disclosed in the embodiment for the convolution operations that improves the overall performance of a CNN. Further, two loading units for weight and pixel loading reduce the latency involved in loading the network parameters into the processing elements. Moreover, a controller has been designed and included in the system architecture to aid the functioning of loading units efficiently.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS
title	Hardware accelerator for efficient convolution processing
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-05T00%3A32%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Rahaman,%20Hafizur&rft.date=2023-10-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11797345B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true