Self-aligned vertical integration of three-terminal memory devices

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through th...

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Hauptverfasser:	Shen, Meihua, Lill, Thorsten, Wu, Hui-Jung, Hoang, John, Pan, Yang, Gunawan, Gereng
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRICITY
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creator	Shen, Meihua Lill, Thorsten Wu, Hui-Jung Hoang, John Pan, Yang Gunawan, Gereng
description	A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11792987B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11792987B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11792987B23</originalsourceid><addsrcrecordid>eNrjZHAKTs1J003MyUzPS01RKEstKslMTsxRyMwrSU0vSizJzM9TyE9TKMkoSk3VLUktys3MA8rmpubmF1UqpKSWZSanFvMwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUkvjQYENDc0sjSwtzJyNjYtQAAGzXMrA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Self-aligned vertical integration of three-terminal memory devices</title><source>esp@cenet</source><creator>Shen, Meihua ; Lill, Thorsten ; Wu, Hui-Jung ; Hoang, John ; Pan, Yang ; Gunawan, Gereng</creator><creatorcontrib>Shen, Meihua ; Lill, Thorsten ; Wu, Hui-Jung ; Hoang, John ; Pan, Yang ; Gunawan, Gereng</creatorcontrib><description>A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.</description><language>eng</language><subject>ELECTRICITY</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231017&DB=EPODOC&CC=US&NR=11792987B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231017&DB=EPODOC&CC=US&NR=11792987B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Shen, Meihua</creatorcontrib><creatorcontrib>Lill, Thorsten</creatorcontrib><creatorcontrib>Wu, Hui-Jung</creatorcontrib><creatorcontrib>Hoang, John</creatorcontrib><creatorcontrib>Pan, Yang</creatorcontrib><creatorcontrib>Gunawan, Gereng</creatorcontrib><title>Self-aligned vertical integration of three-terminal memory devices</title><description>A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAKTs1J003MyUzPS01RKEstKslMTsxRyMwrSU0vSizJzM9TyE9TKMkoSk3VLUktys3MA8rmpubmF1UqpKSWZSanFvMwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUkvjQYENDc0sjSwtzJyNjYtQAAGzXMrA</recordid><startdate>20231017</startdate><enddate>20231017</enddate><creator>Shen, Meihua</creator><creator>Lill, Thorsten</creator><creator>Wu, Hui-Jung</creator><creator>Hoang, John</creator><creator>Pan, Yang</creator><creator>Gunawan, Gereng</creator><scope>EVB</scope></search><sort><creationdate>20231017</creationdate><title>Self-aligned vertical integration of three-terminal memory devices</title><author>Shen, Meihua ; Lill, Thorsten ; Wu, Hui-Jung ; Hoang, John ; Pan, Yang ; Gunawan, Gereng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11792987B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>Shen, Meihua</creatorcontrib><creatorcontrib>Lill, Thorsten</creatorcontrib><creatorcontrib>Wu, Hui-Jung</creatorcontrib><creatorcontrib>Hoang, John</creatorcontrib><creatorcontrib>Pan, Yang</creatorcontrib><creatorcontrib>Gunawan, Gereng</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shen, Meihua</au><au>Lill, Thorsten</au><au>Wu, Hui-Jung</au><au>Hoang, John</au><au>Pan, Yang</au><au>Gunawan, Gereng</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Self-aligned vertical integration of three-terminal memory devices</title><date>2023-10-17</date><risdate>2023</risdate><abstract>A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.</abstract><oa>free_for_read</oa></addata></record>
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title	Self-aligned vertical integration of three-terminal memory devices
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T17%3A05%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Shen,%20Meihua&rft.date=2023-10-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11792987B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true