Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures

A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and th...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Fujita, Yuki, Yamashita, Minoru, Otsuka, Shuzo, Kano, Masahiro, Matsumoto, Kyosuke, Kitamura, Kei, Yamashita, Ryuji
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Fujita, Yuki
Yamashita, Minoru
Otsuka, Shuzo
Kano, Masahiro
Matsumoto, Kyosuke
Kitamura, Kei
Yamashita, Ryuji
description A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11776640B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11776640B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11776640B23</originalsourceid><addsrcrecordid>eNqNjDsOwkAMRNNQIOAO5gCRCKDQ8xM9UCOzccBS4o3W3iCOwY1JgANQzUczb5i8tmgIzktLQdkLPNjuUPRlg51zHFxkUyh9gKgELFD4eK0IlKTLWDeAwd3ZyFkM9AWUAZ11OKzgygaoyjepSaz_i5e09RUad5Saah-eoBbi56_jZFBipTT56SiZ7nenzSGlxl9IG3QkZJfzMctWqzxfztbzxT-bNy4PUJ0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures</title><source>esp@cenet</source><creator>Fujita, Yuki ; Yamashita, Minoru ; Otsuka, Shuzo ; Kano, Masahiro ; Matsumoto, Kyosuke ; Kitamura, Kei ; Yamashita, Ryuji</creator><creatorcontrib>Fujita, Yuki ; Yamashita, Minoru ; Otsuka, Shuzo ; Kano, Masahiro ; Matsumoto, Kyosuke ; Kitamura, Kei ; Yamashita, Ryuji</creatorcontrib><description>A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231003&amp;DB=EPODOC&amp;CC=US&amp;NR=11776640B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20231003&amp;DB=EPODOC&amp;CC=US&amp;NR=11776640B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Fujita, Yuki</creatorcontrib><creatorcontrib>Yamashita, Minoru</creatorcontrib><creatorcontrib>Otsuka, Shuzo</creatorcontrib><creatorcontrib>Kano, Masahiro</creatorcontrib><creatorcontrib>Matsumoto, Kyosuke</creatorcontrib><creatorcontrib>Kitamura, Kei</creatorcontrib><creatorcontrib>Yamashita, Ryuji</creatorcontrib><title>Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures</title><description>A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDsOwkAMRNNQIOAO5gCRCKDQ8xM9UCOzccBS4o3W3iCOwY1JgANQzUczb5i8tmgIzktLQdkLPNjuUPRlg51zHFxkUyh9gKgELFD4eK0IlKTLWDeAwd3ZyFkM9AWUAZ11OKzgygaoyjepSaz_i5e09RUad5Saah-eoBbi56_jZFBipTT56SiZ7nenzSGlxl9IG3QkZJfzMctWqzxfztbzxT-bNy4PUJ0</recordid><startdate>20231003</startdate><enddate>20231003</enddate><creator>Fujita, Yuki</creator><creator>Yamashita, Minoru</creator><creator>Otsuka, Shuzo</creator><creator>Kano, Masahiro</creator><creator>Matsumoto, Kyosuke</creator><creator>Kitamura, Kei</creator><creator>Yamashita, Ryuji</creator><scope>EVB</scope></search><sort><creationdate>20231003</creationdate><title>Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures</title><author>Fujita, Yuki ; Yamashita, Minoru ; Otsuka, Shuzo ; Kano, Masahiro ; Matsumoto, Kyosuke ; Kitamura, Kei ; Yamashita, Ryuji</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11776640B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Fujita, Yuki</creatorcontrib><creatorcontrib>Yamashita, Minoru</creatorcontrib><creatorcontrib>Otsuka, Shuzo</creatorcontrib><creatorcontrib>Kano, Masahiro</creatorcontrib><creatorcontrib>Matsumoto, Kyosuke</creatorcontrib><creatorcontrib>Kitamura, Kei</creatorcontrib><creatorcontrib>Yamashita, Ryuji</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fujita, Yuki</au><au>Yamashita, Minoru</au><au>Otsuka, Shuzo</au><au>Kano, Masahiro</au><au>Matsumoto, Kyosuke</au><au>Kitamura, Kei</au><au>Yamashita, Ryuji</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures</title><date>2023-10-03</date><risdate>2023</risdate><abstract>A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US11776640B2
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
title Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T18%3A19%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Fujita,%20Yuki&rft.date=2023-10-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11776640B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true