Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMS)
A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant...
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| creator | Roy, Anirban Mahatme, Nihaar N |
| description | A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted. |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMS) |
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